In platform application specific integrated circuits (ASICs), defining a section of circuitry in a power domain (i.e., low noise) is commonly problematic where the circuitry interfaces with a noisy power domain. Electrostatic discharge (ESD) issues, and in particular charge device model (CDM) ESD issues, often exist at an interface between the two power domains. A receiving circuit in the power domain can receive power spikes from a transmitting circuit in the noisy power domain. If the power spikes are sufficiently large, transistors in the receiving circuit can be permanently damaged.
A conventional approach to the CDM ESD issue is to include a dedicated clamp circuit at the power domain crossings to protect the receiver circuit. However, positioning of the dedicated clamps cannot be determined until the full chip design is nearly complete and the power domains are reasonably defined. As such, fabrication of silicon is stalled until the final design is close to completion.